1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a circuit for performing a voltage stress test with respect to a DRAM (dynamic random-access memory).
2. Description of the Related Art
In a DRAM, the highest electric field (voltage stress) is applied to the gate insulating film of the transfer gate transistor (cell transistor) of each memory cell having a gate electrode to which a word line is connected. Consequently, there is a high probability that a reliability problem may occur at the gate insulating film. In addition, the refresh cycle is doubled every time devices of a new generation are developed. For this reason, in repeating a normal cycle, the duty ratio at which a high electric field is applied to the word lines is reduced to half for each coming generation.
In a conventional burn-in test of a DRAM, an electric field applied to the gate insulating film of each cell transistor is accelerated by boosting a supply voltage. Since the word lines are sequentially selected, it takes too much time to perform screening of the gate insulating film of each cell transistor. If, therefore, the total time required to screen the gate insulating film of each cell transistor is kept constant even with a change in generation of DRAMs, the burn-in test time is doubled for each coming generation.
Under the circumstances, there is an increasing demand to shorten the burn-in test time of a DRAM. As a measure to meet this demand, it is proposed that a DRAM incorporate a mode in which a larger number of word lines are simultaneously selected than in a normal operation, and a DC voltage is applied to the selected word lines. This mode will be referred to as a quick DC burn-in test mode in order to discriminate it from the conventional normal burn-in test mode. According to a means for realizing this quick DC burn-in test mode, special voltage stress test pads which are not used in a normal operation are additionally arranged on a chip, and a stress voltage is applied to the pads in a burn-in test, thereby simultaneously selecting word lines larger in number than those selected in a normal operation. In this state, a burn-in test is performed.
However, in the burn-in test mode using the above-mentioned special voltage stress test pads, a voltage stress test cannot be performed with respect to a DRAM sealed in a package. In consideration of such a situation, for example, Japanese Patent Application No. 4-225182 discloses a means for realizing a quick DC burn-in test mode. According to this means, by inputting an external control signal, signals on the input or outside side of a word line selection circuit are forcibly controlled to a constant level to simultaneously select all the word lines, thus performing a burn-in test in this state. With this operation, no special voltage stress test pads are required, and the DC burn-in test mode can be set in a wafer state or a packaged state. In a circuit arrangement for setting the quick DC burn-in test mode by externally inputting a control signal, as described above, the number of circuits other than those required for the normal operation mode is preferably minimized to suppress an increase in chip area. In addition, in setting the quick DC burn-in test mode, not only a row decoder but also other circuits must or preferably be controlled simultaneously. There are demands for practical measures to meet these requirements.
On the other hand, a decrease in breakdown voltage between adjacent word lines due to dust must be screened in advance. For example, Japanese Patent Application No. 2-418374 discloses a mode in which the word lines of a word line array are divided into two groups, i.e., an even-numbered word line group and an odd-numbered word line group, and high voltages are simultaneously applied to the two groups, thereby performing a burn-in test by applying a sufficient voltage between adjacent word lines. This mode will be referred to as a quick AC burn-in test mode hereinafter.
FIGS. 1 to 3 show circuits for realizing the quick AC burn-in test mode disclosed in Japanese Patent Application No. 2-418374. The circuit shown in FIG. 1 is used in a DRAM of a bootstrap word line driving scheme, in which a control clock signal .phi..sub.BOOT is caused to rise in the burn-in test mode to transfer charges, prestored in a bootstrap capacitor C.sub.BOOT, to selected word lines WLOi to WLi through n-channel MOS transistors 140 to 142. In the AC burn-in test mode, some of bits A0 to An of an address signal are set at "L" level in both "true and complementary" signals so as to simultaneously select a plurality of NOR type decoders 144 or 145, thereby simultaneously applying a voltage stress to word lines which are not adjacent to each other. In this case, the potential of a bit line BL is fixed at the ground potential through a transfer gate 146 and a pad 147 controlled by a bit line precharging signal .phi..sub.PRE. In each of the circuits shown in FIGS. 2 and 3, special voltage stress test pads 148 to 150 are arranged, and a transfer gate 151 or 152 is connected to one end of each of all word lines WL0i, WL1i, . . . The transfer gates 151 and 152 are selectively driven to select the even-numbered or odd-numbered word line group of the word line array, thereby simultaneously applying a voltage stress to the selected word line group (every other word line in the word line array) through the pad connected to the other end of each of the selected word lines. However, in the burn-in test mode using the special voltage stress test pads, shown in FIGS. 1 to 3, a voltage stress test cannot be performed with respect to a DRAM sealed in a package. In the circuits shown in FIGS. 1 to 3, in realizing the quick AC burn-in test mode, since a normal operation (DRAM operation) cannot be performed, failure modes which can occur in a normal operation but are difficult to predict, such as a decrease in breakdown voltage between adjacent bit lines, cannot be screened in advance.
In order to set the quick DC burn-in test mode in wafer state or a packaged state of a DRAM without requiring special voltage stress test pads, as disclosed in Japanese Patent Application No. 2-418371, a burn-in test must be performed while signals on the input or output side of a word line selecting circuit are forcibly controlled to a constant level by externally inputting a control signal, and a larger number of word lines are simultaneously selected than in a normal operation. As described above, in a circuit arrangement for setting the quick burn-in test mode by externally inputting a control signal, the number of circuits other than those required for the normal operation mode is preferably minimized to reduce an increase in chip area. In addition, in setting the quick burn-in test mode, not only a row decoder but also other circuits must or preferably be controlled simultaneously. Demands have arisen for practical measures to meet these requirements.